One method to form an image on a mask for photolithographic processing is to scan an energy beam, such as an electron beam, across a resist material on the mask. The energy beam is turned on and off as it is scanned across the mask so that the desired image is transferred to the mask pattern.
When transferring the image to the photo or x-ray mask, the alignment of the pattern with regard to a known marker is critical. Since most photolithographic fabrication sequences require multiple levels which precisely overlie one another, it is imperative that the corresponding patterns are correctly aligned. In addition, errors which may be caused by distortions in the energy beam, focus distortions, magnetic distortions, thermal distortions, or physical aberrations such as vibration or stresses may cause non-uniformities within the mask surface as it is being written to. If these anomalies vary between different mask levels, overlapping problems will exist and difficulties will occur with the device performance or yield or design efficiency (e.g., efficient use of wafer area) or all.
In conventional mask writing systems, grid markings are formed in the mask prior to transferring the pattern. These grid markings are typically formed on the outer portions of the mask where no active chips will be formed. The energy beam equipment can then reference from these markings and use this information to ensure the multiple mask levels will be aligned.
Several problems exist with the prior art. The grids are spaced relatively far apart and therefore the resolution is not great enough to eliminate the effects of many of the distortions as described above.
In other conventional circuit writing systems, the grid markings are sometimes formed on the border of the circuit and in places within portions of the circuit. In this case, the circuit layout must be designed around the marks or alternatively, the marks must be placed in less than optimum positions or in less than optimum number of marks (using two or three marks instead of four) on the circuit. In all cases, the alignment marks take up additional valuable surface area. This technique only partially solves the problem of spacing the grid marking too far apart but in turn greatly complicates the circuit design. In many densely packed circuits, such as memory arrays, this loss in surface area is intolerable.
Accordingly, improvements which overcome any or all of the problems are presently desirable.